This invention relates to methods for designing and fabricating digital integrated circuits, and in particular to simulation and analysis of the circuit design in order to detect and eliminate excessive electric field stress on gate oxide of the transistors comprising the digital circuits.
Before an integrated circuit is fabricated, a trial design is analyzed by simulating the operation of the proposed circuits that are to be included within the integrated circuit. Simulation is used to verify correct functional operation of the circuit, as well as to verify correct dynamic timing operation. Gate oxide integrity (GOI) is becoming an increasingly important issue in ULSI reliability. Since the transistor dimensions are typically scaling faster than the supply voltages, the electric fields across the gate oxide are increasing. Excessive electric fields and/or defective gate oxides can lead to Time Dependent Dielectric Breakdown (TDDB) of the oxide.
Signal integrity is one of the key challenges in design and test, now and beyond 100 nm technologies. Rapid technology scaling is causing increased coupling capacitances due to reduced signal to signal spacing and increased distance from the substrate. Among several types of noise, crosstalk noise introduced due to parasitic coupling is predominant in digital designs. Interconnect parasitic coupling has two effects, at least. A first effect is on the delay due to different switching patterns and this affects the performance of the chip besides potential race conditions. A second effect is induced glitches or noise that could cause functional failure by switching logic-states. In the case of designs employing dynamic logic design styles, this problem is more severe due to increased noise sensitivities of pre-charged nodes. In the case of static logic, except for asynchronous signals such as reset/clear and clock nodes, a failure could result only when data inputs connected to storage elements are latched during the active phase of the clock.
Design complexities are increasing with system on chip (SOC) designs and increased length of interconnect at full-chip level is one of the major sources of crosstalk noise problem. This refers to integration of system level functions, for example, many functions in a cellular telephone integrated into one integrated circuit (IC). Typically, SOC designs have CPU cores, memory blocks, logic blocks and possibly analog design blocks, all on one chip. Dynamic simulation of large designs with millions of parasitics is computationally prohibitive; in order reduce computation loads, static noise verification is used. Magnitude of the parasitic coupling, behavior of victim drivers during noise injection and dependency between factors like timing and parasitic coupling are some of key challenges in noise verification.
A commonly used simulator for designing integrated circuits is SPICE, which is available from the University of California at Berkeley, via the Department of Electrica Engineering and Computer Sciences. However, a SPICE simulation of all the nets in an entire chip is far too complex to be practical.
In order to perform a SPICE simulation of a circuit, all of the nodes between every component in the circuit need to be numbered. Then those nodes, the type of components at each node, and the component magnitudes are entered into the SPICE program.
If the circuit which is being simulated is an entire integrated circuit chip, then the number of nodes and corresponding components which need to be entered into the SPICE program is overwhelming. Firstly, the number of nets may be 40,000 in a current typical integrated circuit design. Secondly, for each such net, about seventy discreet components need to be entered because in the actual chip, the net components are distributed. Specifically, each signal line has capacitance which is distributed throughout the line; and each signal line also has a resistance which is distributed throughout the line. To simulate these distributed components, each signal line needs to be represented by a RC ladder circuit which has about two dozen nodes; with each node having a resistor to the next node, a capacitor to ground, and a capacitor to any adjacent signal line.
After all of the nodes and corresponding components for all the nets are entered into the SPICE program, the program operates to determine the voltages which occur on each node in sequential increments of time. Typically, about 1,000 increments of ten picoseconds each are needed to obtain the entire voltage waveform on a node in one net in an integrated circuit chip. To determine the voltages for just one time increment the SPICE program repetitively solves a matrix equation which is of the form [Y] [V]=[1]. Here, Y is an n-xc3x97-n matrix, V is an nxc3x971 matrix, and I is an nxc3x971 matrix; where n is the number of nodes in the circuit. Thus, for a single victim net with twenty aggressor nets, n is (24 nodes per net) xc3x97(21 nets) or 504.
For each increment in time the SPICE program makes about five iterations before it converges on a solution. This iterative process is repeated for each of the subsequent time increments. Using a current state of the art workstation, it takes about ten minutes to perform a SPICE simulation of a single circuit which has 500 nodes and for which a solution is sought for 1,000 time increments. Such a circuit represents a typical victim net with twenty aggressor nets. Consequently, to simulate a chip which has 40,000 nets would take about 400,000 minutes, or more than 270 days to complete!
Accordingly, a primary object of the present invention is to provide a method of designing circuit chips by which the above problems are overcome.
Other objects and advantages will be apparent to those of ordinary skill in the art having reference to the following figures and specification.
Pruning to identify potential victims and associated aggressors forms a key aspect of the methodology of the present invention. In general, and in form the present invention, a method is provided for designing an integrated circuit which contains a plurality of signal lines in close proximity, such that capacitive coupling among the signal lines is operable to induce crosstalk on at least one of the signal lines. Parasitics are extracted from a trial layout of the integrated circuit, and the method further comprises the steps of: grouping the plurality of signal lines into a plurality of aggressor groups; pruning the plurality of signal lines to form a plurality of victim signal lines; building a minimum region network for each victim signal line of the plurality of victim signal lines comprising the respective victim signal line, aggressor signal lines associated with the respective victim signal line, and associated parasitics; simulating the operation of each minimum region network to determine an amount of noise induced on each respective victim signal line by the aggressor signal lines associated with the respective victim signal line, and analyzing the simulation results of each minimum region network to determine if a gate oxide integrity (GOI) violation exists.
In another form of the invention, an integrated circuit is fabricated according to the modified trial layout.
In another form of the invention, a computer system is provided which as a mass storage device that holds a design program for designing an integrated circuit according to the above described method.
These and other features of the invention that will be apparent to those skilled in the art from the following detailed description of the invention, taken together with the accompanying drawings.